1. Field of the Invention
The present invention relates to an optical reception apparatus for receiving a phase modulated signal light, and in particular, to a technology for demodulating a signal light which is differential phase-shift keying modulated using a quadrature-phase component.
2. Description of the Related Art
In recent years, there have been increased demands for introducing a 40 Gbit/s optical transmission system of next generation, and furthermore, such a system is required to achieve a transmission distance and frequency utilization efficiency equivalent to those of a 10 Gbit/s system. As means for realizing such a system, there has been actively performed the search and development of the RZ (Return to Zero)-DPSK (Differential Phase Shift Keying) modulation or the CSRZ (Carrier Suppressed Return to Zero)-DPSK modulation, which is a modulation format with excellent optical signal-to-noise ratio (OSNR) efficiency and excellent non-linear tolerance, in comparison with a NRZ (Non Return to Zero) modulation format which has been applied to a conventional system of 10 Gbit/s or lower. Moreover, in addition to the above modulation format, there has also been actively performed the search and development of a phase modulation format such as the RZ-DQPSK (Differential Quadrature Phase-Shift Keying) modulation or a CSRZ-DQPSK modulation, which has a feature of narrow spectrum (high frequency utilization efficiency) (refer to Japan National Phase Patent Publication No. 2004-516743 and Japanese Unexamined Patent Publication No. 8-84165).
FIG. 9 is a diagram showing a configuration example of an optical transmission apparatus and an optical reception apparatus to which a RZ-DQPSK or a CSRZ-DQPSK modulation format (to be referred to as (CS)RZ-DQPSK modulation format, hereunder) is adopted. Further, FIG. 10 is a graph showing states of optical intensity and optical phase in the case where a (CS)RZ-DQPSK modulated optical signal is transmitted/received.
In FIG. 9, an optical transmission apparatus 210 comprises, for example, a transmission data processing section 211, a 1:2 demultiplexing section (DEMUX) 212, a CW light source 213, a π/2 phase shifter 214, two phase modulators 215A and 215B, and a RZ pulsing intensity modulator 216.
To be specific, the transmission data processing section 211 is provided with a function as a framer for framing input data and a function as a FEC (Forward Error Correction) encoder for giving an error-correcting code, and also, is provided with a function as a DQPSK pre-coder for performing the coding processing reflected with information of a difference between a code of 1 bit before and a current code.
The 1:2 demultiplexing section 212 demultiplexes the coded data from the transmission data processing section 211 into coded data #1 and coded data #2 in dual series of ½ times a bit rate.
The CW light source 213 is for outputting a continuous light, and the output continuous light is separated into two, so that one of the separated lights is input to the phase modulator 215A, and the other is input to the phase modulator 215B via the π/2 phase shifter 214.
The phase modulator 215A modulates the continuous light from the CW light source 213 using the coded data #1 which is one of the dual series demultiplexed by the 1:2 demultiplexing section 212, to output an optical signal in which a binary optical phase (0rad or πrad) thereof carries information. Further, the phase modulator 215B is input with a light which is obtained by phase shifting the continuous light from the CW light source 213 by π/2 in the π/2 phase shifter 214, and modulates this input light using the coded data #2. which is the other of the dual series demultiplexed by the 1:2 demultiplexing section 212, to output an optical signal in which a binary optical phase (π/2rad or 3 π/2rad) thereof carries information. The lights modulated by the phase modulators 215A and 215B are multiplexed with each other, to be output to the latter staged RZ pulsing intensity modulator 216. Namely, the modulated lights from the phase modulators 215A and 215B are multiplexed with each other, so that an optical signal in which optical intensity thereof is fixed but a four-valued optical phase thereof carries information (refer to the lower stage of FIG. 10), that is, a DQPSK modulated optical signal, is sent to the RZ pulsing intensity modulator 216.
The RZ pulsing intensity modulator 216 is for RZ pulsing the DQPSK modulated signal from the phase modulators 215A and 215B. In particular, an optical signal which is RZ pulsed using a clock drive signal having a frequency same as a bit rate of data #1 and data #2, and also having the amplitude of 1 time an extinction voltage (Vπ), is called a RZ-DQPSK signal, and further, an optical signal which is RZ pulsed using a clock drive signal having a frequency half the bit rate of data #1 and data #2, and also having the amplitude of 2 times the extinction voltage (Vπ), is called a CSRZ-DQPSK signal.
Further, an optical reception apparatus 230 is connected to the optical transmission apparatus 210 via a transmission path 220 and an optical repeater 221, to perform the reception processing on the (CS)RZ-DQPSK signal from the optical transmission apparatus 210, which has been repeatedly transmitted, and comprises, for example, a branching section 231 that branches the received optical signal into two, and also comprises, on optical signal paths thereof through which the branched optical signals are respectively propagated, delay interferometers 232A and 232B, and photoelectric converting sections 233A and 233B. Further, the optical reception apparatus 230 comprises a clock recovery (CR) circuit 234 for recovering a clock signal based on a data signal from the photoelectric converting section 233A, a 2:1 multiplexing section (MUX) 235 that multiplexes data signals from the photoelectric converting sections 233A and 233B, and a received data processing section 236.
To be specific, the delay interferometers 232A and 232B receive respectively the optical signals which are obtained by branching the (CS)RZ-DQPSK signal transmitted through the transmission path 220 and the optical repeater 221 into two by the branching section 231. The delay interferometer 232A makes a delay component per 1 bit time and a component phase controlled of π/4rad to interfere (delay interfere) with each other, to output interference results thereof as two outputs. Further, the delay interferometer 232B makes a delay component per 1 bit time and a component phase controlled of −π/4rad (which is shifted by π/2rad to the phase controlled component in the delay interferometer 232A) to interfere (delay interfere) with each other, to output interference results thereof as two outputs. Here, the delay interferometers 232A and 232B each is configured by a Mach-Zehnder interferometer, and each Mach-Zehnder interferometer is configured so that one of branched waveguides is formed to be longer than the other branched waveguide by the propagation length equivalent to the 1 bit time, and also, is formed with an electrode for phase controlling the optical signal propagated through the other branched waveguide.
The photoelectric converting sections 232A and 232B are respectively configured by dual pin photodiodes for receiving the respective outputs from the delay interferometers 232A and 232B to perform differential photoelectric conversion detections. Incidentally, the received signals detected respectively by the photoelectric converting sections 233A and 233B are appropriately amplified by amplifiers.
The clock recovery circuit 234 recovers the clock signal from the received signal which is subjected to the differential photoelectric conversion detection in the photoelectric converting section 232A, to output it to the 2:1 multiplexing section 235.
The 2:1 multiplexing section 235 multiplexes data (for example, an in-phase component 1) output from the photoelectric converting section 233A and data (for example, a quadrature-phase component Q) output from the photoelectric converting section 233B in accordance with timing of the clock signal from the clock recovery circuit 234, to convert the multiplexed data into the data signal before DQPSK modulation.
The received data processing section 236 is provided with a function as a framer for framing the data signal output from the 2:1 multiplexing section 235, a function as a decoder for decoding the given error-correcting code, and the like.
Generally, in the case of performing the transmission of a differential phase shift keying modulated signal light, for the decoding processing of a transmission light, a synchronization detection using a framer is required for achieving the synchronization with an original signal (transmitted signal). For example, in the optical reception apparatus 230 corresponding to the (CS)RZ-DQPSK modulation format shown in FIG. 9, the synchronization detection by the framer function of the received data processing section 236 is performed on the data signal which is obtained by multiplexing the output signals from the respective photoelectric converting sections 233A and 233B, in the 2:1 multiplexing section 235.
However, in the configuration of the optical reception apparatus 230 as described in the above, a phase relation between the data signals output from the photoelectric converting sections 233A and 233B is merely in a relatively quadrature-phase state, and which of the data signals corresponds to the in-phase component I or the quadrature-phase component Q depends on operating conditions of the respective delay interferometers 232A and 232B. Therefore, for example in the case where the designing of the latter staged synchronization detection processing is made provided that the component I at the transmission time corresponds to the data signal from the photoelectric converting section 233A and the component Q at the transmission time corresponds to the data signal from the photoelectric converting section 233B, there is a problem in that the inversion or the shifting occurs between the component I and the component Q. Further, in the 2:1 multiplexing section 235, since the respective data signals are multiplexed with each other in accordance with the timing of the clock signal recovered in the clock recovery circuit 234, there is a problem in that the shifting occurs also in time strings of the components I and Q depending on the phase relation between the data signals and the-clock signal.
To be specific, explaining a factor of the inversion between the component I and the component Q, in each of the delay interferometers 232A and 232B, as described above, the two quadrature-phase components of the input light are separated, and thereafter, a phase change of the transmitted signal is detected based on a difference between the optical phases obtained by making the delay component per 1 bit time and the component phase controlled of ±π/4rad to interfere (delay interfere) with each other, so that the detection results are output as the signal components. Therefore, logic of the component I or the component Q may be inverted depending on changes in wavelengths or phases of the lights input to the delay interferometers 232A and 232B, or on state changes in the delay interferometers 232A and 232B for when the two quadrature-phase components are separated. Specifically, the conditions of the delay interferometers 232A and 232B can be optimized by feedback controlling delay amounts or the like thereof using the output signals from the photoelectric converting sections 233A and 233B respectively corresponding to the delay interferometers 232A and 232B. However, even if the feedback control in the delay interferometer 232A is same as that in the delay interferometer 232B, the difference between the optical phases detected in the delay interferometers 232A and 232B cannot be exactly the same. Thus, the inversion between the component I and the component Q occurs depending on the operating conditions of the delay interferometers 232A and 232B.
Further, explaining a factor of the shifting between the components I and Q, even if the similar feedback controls are performed to optimize the conditions of the delay interferometers 232A and 232B for when the two quadrature-phase components are separated, the phase states exactly the same as those on the transmission side cannot be achieved, and for example even if the designing is made provided that the component I is output to the delay interferometer 232A, there occurs a state where the component Q is output thereto. Incidentally, in this state, the component I is output to the delay interferometer 232B. Furthermore, in the clock recovery circuit 234, the clock signal is extracted based on a frequency component of one of the input signals to the 2:1 multiplexing section 235 (in the configuration example of FIG. 9, the signal sent from the photoelectric converting section 233A to the 2:1 multiplexing section 235), and therefore, a relative phase relation between the clock signal output from the clock recovery circuit 234 and the two input signals to the 2:1 multiplexing section 235 is not clearly defined. As a result of this, there occurs a phenomenon in which the component I and the component Q are shifted to each other due to the phase relation between the data signals and the clock signal, which are input to the 2:1 multiplexing section 235.
Moreover, in addition to the shifting between the components I and Q, also one bit delay may occur. Explaining a factor of the one bit delay in this case, sometimes, a circuit is mounted for separating the input signal to the received data processing section into 1:16 or the like, for example in order to decrease a speed of an electric signal to be processed in the received data processing section 236 on the latter stage of the 2:1 multiplexing section 235. In such a configuration, if the shifting between the components I and Q occurs in the output signal of the 2:1 multiplexing section 235, the further one bit delay occurs with probability ½.
Collecting up occurrence states of the inversion and the shifting between the components I and Q, the next table 1 is obtained. Incidentally, herein, the state where the component I is output from the delay interferometer 233A side and the component Q is output from the delay interferometer 233B side is assumed to be a correct reception state.
TABLE 1delay interferometer233A side outputQ QĪIdelayQXX◯⊚interferometer QXX◯◯233B sideĪΔΔXXoutputI⋄ΔXX
In the above table 1, the double circle mark indicates the correct reception state. The single circle mark indicates a state where the logic inversion needs to be controlled. The triangular mark indicates a state where the logic inversion and also the bit swap need to be controlled. The rhomboid-shaped mark indicates a state where the bit swap needs to be controlled. The cross mark indicates a state where the optimization of the delay interferometer needs to be performed. Incidentally, the control of the bit swap is a control for swapping respective former and latter bits corresponding to the components I and Q with each other, in the case where, as shown in FIG. 11(A) for example, bit strings of the data signal output from the 2:1 multiplexing section 235 are in a state as shown in the lower stage relative to bit strings thereof (herein, for the simplicity, 4 bit strings) at the transmission time on the upper stage. Further, in the case where, as shown in FIG. 11(B) for example, the one bit delay occurs in the state shown in the lower stage of FIG. 11(A), such a control for shifting the bit corresponding to the component Q while holding the bit corresponding to the component I is included in the control of the bit swap.
For the control of the logic inversion or the bit swap for the data signal output from the 2:1 multiplexing section 235, for example, it is considered that the dedicated designing is made corresponding to the DQPSK modulation format as the framer function of the received data processing section 236, so that the digital processing is executed in the framer. However, in such a dedicated framer, the ultra-high speed logical processing is required. Therefore, in order to realize such a dedicated framer, there are caused problems of an increase of power consumption, an increase of chip area and an increase of cost and the like. Such problems are not limited to the DQPSK modulation format and are common to the demodulating processing of the signal light which is differential phase shift keying modulated using the quadrature-phase component.